The "IEEE Standard for Binary Floating-Point Arithmetic" (IEEE 754 Standard) defines a format called double extended which specifies a representation with a one bit sign, 15 or more bits of exponent, and 64 or more bits of significand. There has been discussions among the standards committee of adopting a quad word format which is more restrictive but is a subset of the double extended format. Several manufacturers including Hewlett-Packard's PA-RISC 1.1 Architecture and IBM S/390 have adopted a specific quad word format which contains one bit of sign information, 15 bits of exponent, and 113 bits of significand where the most significant bit is implied. This format requires 128 bits or one quad word to represent an operand.
Most floating point units are not optimized for the quad word format and instead are optimized for the frequently used double word format. The quad word format operands must be partitioned into the hardware implemented format and then multiple smaller operations are performed to accomplish the overall quad word format operation. One floating operation which is typically supported in this fashion is the multiplication operation for quad word format.
Note that the definition of quad word format that is referred to by Hewlett-Packard's PA-RISC 1.1 Architecture is called binary extended format by the S/390 Architecture, but they are identical except for the representation of signaling NaN and quiet NaN which is not important for this discussion. S/390 Architecture also supports a unique hexadecimal based format which has a short (word), long (double word), and extended (quad word) formats. In typical S/390 floating point units hexadecimal double word precision is optimized in hardware, which is similar to other manufacturers optimizing for IEEE 754 standard double word format since both formats require 64 bits to represent. Hexadecimal double format contains one bit of sign information, seven bits of exponent, and a 56 bit significand. S/390 floating point unit dataflows are typically optimized for 56 bit operands. The multiplier, if used for other purposes such as for division operations, may have some additional guard bits. In a performance optimized multiplier implementation one of the operands, the multiplier, is not extended by any guard bits since one additional bit has a dramatic effect on the overall delay of the counter tree. But, the other operand, the multiplicand, has a less substantial effect on the delay of the counter tree and can easily be extended by one or two hex digits. Typical S/390 multipliers have a multiplier which is 56 bits and a multiplicand which is 60 or 64 bits (see for instance "CMOS floating-point unit for the S/390 Parallel Enterprise Server G4," E. M. Schwarz, L. Sigal, T. J. McPherson, IBM Journal of Research and Development, Vol. 41, No. 4/5, July/September 1997, pp.475-488.)
The method of optimizing the binary extended format (quad word format) to a S/390 floating point unit for a system where the 56 bit significand dataflow is slightly less than half the 113 bit significand of the binary extended format has not been found since the adoption of the IEEE standard over a decade ago. In particular, the present invention is concerned with implementing the multiplication operation for binary quad word format on a typical S/390 multiplier.